> On Tue, Jan 20, 2026 at 10:07:33AM +0000, Yeoreum Yun wrote: > > Hi Mark, > > > > > On Mon, Jan 19, 2026 at 10:32:11PM +0000, Yeoreum Yun wrote: > > > > > On Mon, Dec 15, 2025 at 09:56:04AM +0000, Yeoreum Yun wrote: > > > > > > > On Sun, 14 Dec 2025 11:22:48 +0000, > > > > > > > Yeoreum Yun <[email protected]> wrote: > > > > > > > > > > > > > > > > Apply the FEAT_LSUI instruction to emulate the deprecated swpX > > > > > > > > instruction, so that toggling of the PSTATE.PAN bit can be > > > > > > > > removed when > > > > > > > > LSUI-related instructions are used. > > > > > > > > > > > > > > > > Signed-off-by: Yeoreum Yun <[email protected]> > > > > > > > > > > > > > > It really begs the question: what are the odds of ever seeing a > > > > > > > CPU > > > > > > > that implements both LSUI and AArch32? > > > > > > > > > > > > > > This seems extremely unlikely to me. > > > > > > > > > > > > Well, I'm not sure how many CPU will have > > > > > > both ID_AA64PFR0_EL1.EL0 bit as 0b0010 and FEAT_LSUI > > > > > > (except FVP currently) -- at least the CPU what I saw, > > > > > > most of them set ID_AA64PFR0_EL1.EL0 as 0b0010. > > > > > > > > > > Just to make sure I understand you, you're saying that you have seen > > > > > a real CPU that implements both 32-bit EL0 *and* FEAT_LSUI? > > > > > > > > > > > If you this seems useless, I don't have any strong comments > > > > > > whether drop patches related to deprecated swp instruction parts > > > > > > (patch 8-9 only) or not. > > > > > > (But, I hope to pass this decision to maintaining perspective...) > > > > > > > > > > I think it depends on whether or not the hardware exists. Marc thinks > > > > > that it's extremely unlikely whereas you appear to have seen some (but > > > > > please confirm). > > > > > > > > What I meant was not a 32-bit CPU with LSUI, but a CPU that supports > > > > 32-bit EL0 compatibility (i.e. ID_AA64PFR0_EL1.EL0 = 0b0010). > > > > My point was that if CPUs implementing LSUI do appear, most of them > > > > will likely > > > > continue to support the existing 32-bit EL0 compatibility that > > > > the majority of current CPUs already have. > > > > > > That doesn't really answer Will's question. Will asked: > > > > > > Just to make sure I understand you, you're saying that you have seen a > > > real CPU that implements both 32-bit EL0 *and* FEAT_LSUI? > > > > > > IIUC you have NOT seen any specific real CPU that supports this, and you > > > have been testing on an FVP AEM model (which can be configured to > > > support this combination of features). Can you please confirm? > > > > > > I don't beleive it's likely that we'll see hardware that supports > > > both FEAT_LSUI and AArch32 (at EL0). > > > > Yes. I've tested in FVP model. and the latest of my reply said > > I confirmed that Marc's and your view was right. > > It's probably still worth adding something to the cpufeature stuff to > WARN() if we spot both LSUI and support for AArch32. >
On second thought, while a CPU that implements LSUI is unlikely to support AArch32 compatibility, I don't think LSUI requires the absence of AArch32. These two are independent features (and in fact our FVP reports/supports both). Given that, I'm not sure a WARN is really necessary. Would it be sufficient to just drop the patch for swpX instead? Thanks! -- Sincerely, Yeoreum Yun
