On Mon, Dec 15, 2025 at 09:56:04AM +0000, Yeoreum Yun wrote: > Hi, > > > On Sun, 14 Dec 2025 11:22:48 +0000, > > Yeoreum Yun <[email protected]> wrote: > > > > > > Apply the FEAT_LSUI instruction to emulate the deprecated swpX > > > instruction, so that toggling of the PSTATE.PAN bit can be removed when > > > LSUI-related instructions are used. > > > > > > Signed-off-by: Yeoreum Yun <[email protected]> > > > > It really begs the question: what are the odds of ever seeing a CPU > > that implements both LSUI and AArch32? > > > > This seems extremely unlikely to me. > > Well, I'm not sure how many CPU will have > both ID_AA64PFR0_EL1.EL0 bit as 0b0010 and FEAT_LSUI > (except FVP currently) -- at least the CPU what I saw, > most of them set ID_AA64PFR0_EL1.EL0 as 0b0010.
Just to make sure I understand you, you're saying that you have seen a real CPU that implements both 32-bit EL0 *and* FEAT_LSUI? > If you this seems useless, I don't have any strong comments > whether drop patches related to deprecated swp instruction parts > (patch 8-9 only) or not. > (But, I hope to pass this decision to maintaining perspective...) I think it depends on whether or not the hardware exists. Marc thinks that it's extremely unlikely whereas you appear to have seen some (but please confirm). Will
