Hi guys, v1: fixed whitespace damage in 1/2 and applied Adrian's comment to 2/2.
There is a problem between the PT driver and the AUX allocator that results in smaller buffers consisting of 2 high-order regions, which also means only 2 possibilities of where PMI gets generated and where tracing stops. This is not good enough for double buffering: when we get a PMI mid-buffer, we update the ->aux_head etc and immediately start a new transaction while observing ->aux_tail to still be zero, which makes the PT driver put a stop bit at the end of the buffer. However quick userspace is to update the ->aux_tail, that second transaction/PERF_RECORD_AUX ends up truncated. The proposed solution here is to set up attr.aux_watermark to a quarter of the buffer. Unfortunately, at the moment, the PT driver is not equipped to deal with aux_watermark that's smaller than the AUX allocation order. I could fix this in the driver itself, but, seeing as it's the only PMU that actually uses the 'order' from AUX allocations, I'd rather fix the allocator instead, which is done in patch 1/2. Patch 2/2 could be replaced by instead changing the in-kernel aux_watermark default, but that may interfere with PMU drivers that don't ignore said watermark / handle->wakeup (afaict, that's only arm_spe). Alexander Shishkin (2): perf: Cap allocation order at aux_watermark perf intel-pt: Use aux_watermark kernel/events/ring_buffer.c | 34 +++++++++++++++-------------- tools/perf/arch/x86/util/intel-pt.c | 6 +++++ 2 files changed, 24 insertions(+), 16 deletions(-) -- 2.30.2
