> This is a timing issue, isn't it? How are we synchronising, other than > by delaying for a (bus-dependant) period? The characteristics of each > bus are known so a number can be assigned for "one bus cycle", without > having to use the bus.
The characteristics of the bus are not known. It could be anything between 6 and about 16MHz. The way you read the bus clock is system dependant. The underlying problem is really that over time some of the hardware has moved from the ISA world into the chipsets. That is why I sent Ingo the patches for inb_pit/inb_pic and to split ISA 8390 and non ISA 8390 support. Someone has to tackle the CMOS but we are then in a position to relegant port 0x80 timing use to ISA systems where it is fine. Alan -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
