> -----Original Message----- > From: Tian, Kevin [mailto:kevin.t...@intel.com] > Sent: Thursday, March 18, 2021 4:43 PM > To: Longpeng (Mike, Cloud Infrastructure Service Product Dept.) > <longpe...@huawei.com>; Nadav Amit <nadav.a...@gmail.com> > Cc: chenjiashang <chenjiash...@huawei.com>; David Woodhouse > <dw...@infradead.org>; io...@lists.linux-foundation.org; LKML > <linux-kernel@vger.kernel.org>; alex.william...@redhat.com; Gonglei (Arei) > <arei.gong...@huawei.com>; w...@kernel.org > Subject: RE: A problem of Intel IOMMU hardware ？ > > > From: Longpeng (Mike, Cloud Infrastructure Service Product Dept.) > > <longpe...@huawei.com> > > > > > > > -----Original Message----- > > > From: Tian, Kevin [mailto:kevin.t...@intel.com] > > > Sent: Thursday, March 18, 2021 4:27 PM > > > To: Longpeng (Mike, Cloud Infrastructure Service Product Dept.) > > > <longpe...@huawei.com>; Nadav Amit <nadav.a...@gmail.com> > > > Cc: chenjiashang <chenjiash...@huawei.com>; David Woodhouse > > > <dw...@infradead.org>; io...@lists.linux-foundation.org; LKML > > > <linux-kernel@vger.kernel.org>; alex.william...@redhat.com; Gonglei > > (Arei) > > > <arei.gong...@huawei.com>; w...@kernel.org > > > Subject: RE: A problem of Intel IOMMU hardware ？ > > > > > > > From: iommu <iommu-boun...@lists.linux-foundation.org> On Behalf > > > > Of Longpeng (Mike, Cloud Infrastructure Service Product Dept.) > > > > > > > > > 2. Consider ensuring that the problem is not somehow related to > > > > > queued invalidations. Try to use __iommu_flush_iotlb() instead > > > > > of > > > qi_flush_iotlb(). > > > > > > > > > > > > > I tried to force to use __iommu_flush_iotlb(), but maybe something > > > > wrong, the system crashed, so I prefer to lower the priority of > > > > this > > operation. > > > > > > > > > > The VT-d spec clearly says that register-based invalidation can be > > > used only > > when > > > queued-invalidations are not enabled. Intel-IOMMU driver doesn't > > > provide > > an > > > option to disable queued-invalidation though, when the hardware is > > capable. If you > > > really want to try, tweak the code in intel_iommu_init_qi. > > > > > > > Hi Kevin, > > > > Thanks to point out this. Do you have any ideas about this problem ? I > > tried to descript the problem much clear in my reply to Alex, hope you > > could have a look if you're interested. > > > > I agree with Nadav. Looks this implies some stale paging structure cache > entry (e.g. > PMD) is not invalidated properly. It's better if Baolu can reproduce this > problem in > his local environment and then do more debug to identify whether it's a > software or > hardware defect. > > btw what is the device under test? Does it support ATS? >
The device is our offload card, it does not support ATS cap. > Thanks > Kevin
