Add crypto engine (CE) and CE BAM related nodes and definitions to
"sm8250.dtsi".
Cc: Thara Gopinath <thara.gopin...@linaro.org>
Cc: Bjorn Andersson <bjorn.anders...@linaro.org>
Cc: Rob Herring <robh...@kernel.org>
Cc: Andy Gross <agr...@kernel.org>
Cc: Herbert Xu <herb...@gondor.apana.org.au>
Cc: David S. Miller <da...@davemloft.net>
Cc: Stephen Boyd <sb...@kernel.org>
Cc: Michael Turquette <mturque...@baylibre.com>
Cc: linux-...@vger.kernel.org
Cc: linux-cry...@vger.kernel.org
Cc: devicet...@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: bhupesh.li...@gmail.com
Signed-off-by: Bhupesh Sharma <bhupesh.sha...@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 36 ++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi
b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 947e1accae3a..4f7482dbc2bf 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -3744,6 +3744,42 @@ cpufreq_hw: cpufreq@18591000 {
#freq-domain-cells = <1>;
};
+
+ cryptobam: dma@1dc4000 {
+ compatible = "qcom,bam-v1.7.0";
+ reg = <0 0x01dc4000 0 0x24000>;
+ interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rpmhcc RPMH_CE_CLK>;
+ clock-names = "bam_clk";
+ num-channels = <2>;
+ qcom,num-ees = <1>;
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ qcom,controlled-remotely = <1>;
+ iommus = <&apps_smmu 0x584 0x0011>,
+ <&apps_smmu 0x594 0x0011>,
+ <&apps_smmu 0x592 0>,
+ <&apps_smmu 0x598 0>,
+ <&apps_smmu 0x599 0>,
+ <&apps_smmu 0x59F 0>;
+ };
+
+ crypto: crypto@1dfa000 {
+ compatible = "qcom,crypto-v5.5";
+ reg = <0 0x01dfa000 0 0x6000>;
+ clocks = <&gcc GCC_CE1_AHB_CLK>,
+ <&gcc GCC_CE1_AHB_CLK>,
+ <&rpmhcc RPMH_CE_CLK>;
+ clock-names = "iface", "bus", "core";
+ dmas = <&cryptobam 6>, <&cryptobam 7>;
+ dma-names = "rx", "tx";
+ iommus = <&apps_smmu 0x584 0x0011>,
+ <&apps_smmu 0x594 0x0011>,
+ <&apps_smmu 0x592 0>,
+ <&apps_smmu 0x598 0>,
+ <&apps_smmu 0x599 0>,
+ <&apps_smmu 0x59F 0>;
+ };
};
timer {
--
2.29.2
