> > I think the case before us that Arthur is dealing with is a
> > counterexample for this: there's nothing bus-specific about it all.
> > The issue is related to reordering of DMAs within the Altix system
> > fabric, after they've left the PCI world. This issue would be present
> > no matter what kind of host bridge you hook up to the system fabric,
> > be it PCI-X, PCIe, ISA, MCA or whatever.
> But it is: for performance reasons, the Altix boxes have a rather non
> standard PCI bridge implementation that gives relaxed ordering on the
> PCI bus.
I don't think this is accurate. As I understand things, the reordering
happens within the Altix system interconnect -- nothing to do with the
PCI bridge hanging off this fabric. It is "platform" behavior and I
think is properly handled within the dma_ API, which exists to
abstract platforms.
> This behaviour was later standardised to some degree in PCIe,
> so you could argue they actually have an altix specific PCI bus (PCIa
> anyone?). Regardless, other manufacturers are probably going to demand
> something equivalent to this based on the PCIe standard, so we should be
> ready for it, hence the desire for the bus specific attributes.
But:
a) The Altix has PCI-X, not PCIe, so having something PCIe-specific
is not a solution for this case; and
b) the PCIe behavior is opt-in, in the sense that you have to
specifically ask for looser ordering, while the Altix is loosely
ordered unless you ask for this "flush" property. So I don't
think the same attribute will work for both cases.
- R.
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to [EMAIL PROTECTED]
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
