The constant LITEX_REG_SIZE is renamed to the more descriptive
LITEX_SUBREG_ALIGN (LiteX CSR subregisters are located at 32-bit
aligned MMIO addresses).
NOTE: this is a non-functional change.
Signed-off-by: Gabriel Somlo <gso...@gmail.com>
---
include/linux/litex.h | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/include/linux/litex.h b/include/linux/litex.h
index 918bab45243c..c63a7e1a337c 100644
--- a/include/linux/litex.h
+++ b/include/linux/litex.h
@@ -20,10 +20,12 @@
* Supporting other configurations will require extending the logic in this
* header and in the LiteX SoC controller driver.
*/
-#define LITEX_REG_SIZE 0x4
#define LITEX_SUBREG_SIZE 0x1
#define LITEX_SUBREG_SIZE_BIT (LITEX_SUBREG_SIZE * 8)
+/* LiteX subregisters of any width are always aligned on a 4-byte boundary */
+#define LITEX_SUBREG_ALIGN 0x4
+
static inline void _write_litex_subregister(u32 val, void __iomem *addr)
{
writel((u32 __force)cpu_to_le32(val), addr);
@@ -36,11 +38,11 @@ static inline u32 _read_litex_subregister(void __iomem
*addr)
#define WRITE_LITEX_SUBREGISTER(val, base_offset, subreg_id) \
_write_litex_subregister(val, (base_offset) + \
- LITEX_REG_SIZE * (subreg_id))
+ LITEX_SUBREG_ALIGN * (subreg_id))
#define READ_LITEX_SUBREGISTER(base_offset, subreg_id) \
_read_litex_subregister((base_offset) + \
- LITEX_REG_SIZE * (subreg_id))
+ LITEX_SUBREG_ALIGN * (subreg_id))
/*
* LiteX SoC Generator, depending on the configuration, can split a single
--
2.26.2
