[PATCH 2/3] arm64: cpufeature: Add a filter function to cpufeature

[Srinivas Ramana]

Add a filter function to cpufeature so that it can be used
when dynamic control of the feature is required.

Signed-off-by: Ajay Patil <pa...@qti.qualcomm.com>
Signed-off-by: Prasad Sodagudi <psoda...@codeaurora.org>
Signed-off-by: Srinivas Ramana <sram...@codeaurora.org>
---
 arch/arm64/include/asm/cpufeature.h |  8 +++++++-
 arch/arm64/kernel/cpufeature.c      | 15 ++++++++++-----
 2 files changed, 17 insertions(+), 6 deletions(-)

diff --git a/arch/arm64/include/asm/cpufeature.h 
b/arch/arm64/include/asm/cpufeature.h
index 9a555809b89c..81a5c97d647d 100644
--- a/arch/arm64/include/asm/cpufeature.h
+++ b/arch/arm64/include/asm/cpufeature.h
@@ -61,6 +61,7 @@ struct arm64_ftr_bits {
        u8              shift;
        u8              width;
        s64             safe_val; /* safe value for FTR_EXACT features */
+       s64             (*filter)(const struct arm64_ftr_bits *ftrp, s64 fval);
 };
 
 /*
@@ -566,7 +567,12 @@ cpuid_feature_extract_field(u64 features, int field, bool 
sign)
 
 static inline s64 arm64_ftr_value(const struct arm64_ftr_bits *ftrp, u64 val)
 {
-       return (s64)cpuid_feature_extract_field_width(val, ftrp->shift, 
ftrp->width, ftrp->sign);
+       s64 fval = (s64)cpuid_feature_extract_field_width(val, ftrp->shift,
+                                       ftrp->width, ftrp->sign);
+
+       if (ftrp->filter)
+               fval = ftrp->filter(ftrp, fval);
+       return fval;
 }
 
 static inline bool id_aa64mmfr0_mixed_endian_el0(u64 mmfr0)
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 7ffb5f1d8b68..b2ffa9eaaaff 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -132,23 +132,28 @@ DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, 
ARM64_NCAPS);
 EXPORT_SYMBOL(cpu_hwcap_keys);
 
 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, 
SAFE_VAL) \
-       {                                               \
                .sign = SIGNED,                         \
                .visible = VISIBLE,                     \
                .strict = STRICT,                       \
                .type = TYPE,                           \
                .shift = SHIFT,                         \
                .width = WIDTH,                         \
-               .safe_val = SAFE_VAL,                   \
-       }
+               .safe_val = SAFE_VAL
 
 /* Define a feature with unsigned values */
 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
-       __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, 
SAFE_VAL)
+       {__ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, 
SAFE_VAL), }
 
 /* Define a feature with a signed value */
 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
-       __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, 
SAFE_VAL)
+       {__ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, 
SAFE_VAL), }
+
+/* Define a feature with a filter function to process the field value */
+#define FILTERED_ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, 
SAFE_VAL, filter_fn) \
+       {                                                                       
                \
+               __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, 
SAFE_VAL),        \
+               .filter = filter_fn,                                            
                \
+       }
 
 #define ARM64_FTR_END                                  \
        {                                               \
-- 
2.7.4