On Tue, Dec 22, 2020 at 9:14 PM Weiyi Lu <weiyi...@mediatek.com> wrote:
>
> Add MT8192 basic clock providers, include topckgen, apmixedsys,
> infracfg and pericfg.
>
> Signed-off-by: Weiyi Lu <weiyi...@mediatek.com>
> ---
> drivers/clk/mediatek/Kconfig | 8 +
> drivers/clk/mediatek/Makefile | 1 +
> drivers/clk/mediatek/clk-mt8192.c | 1326
> +++++++++++++++++++++++++++++++++++++
> drivers/clk/mediatek/clk-mux.h | 15 +
> 4 files changed, 1350 insertions(+)
> create mode 100644 drivers/clk/mediatek/clk-mt8192.c
>
<snip>
> diff --git a/drivers/clk/mediatek/clk-mux.h b/drivers/clk/mediatek/clk-mux.h
> index f5625f4..afbc7df 100644
> --- a/drivers/clk/mediatek/clk-mux.h
> +++ b/drivers/clk/mediatek/clk-mux.h
> @@ -77,6 +77,21 @@ struct mtk_mux {
> _width, _gate, _upd_ofs, _upd, \
> CLK_SET_RATE_PARENT)
>
> +#define MUX_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
> + _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
> + _upd_ofs, _upd, _flags) \
> + GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
> + _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
> + 0, _upd_ofs, _upd, _flags, \
> + mtk_mux_clr_set_upd_ops)
> +
> +#define MUX_CLR_SET_UPD(_id, _name, _parents, _mux_ofs,
> \
> + _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
> + _upd_ofs, _upd) \
> + MUX_CLR_SET_UPD_FLAGS(_id, _name, _parents, \
> + _mux_ofs, _mux_set_ofs, _mux_clr_ofs, _shift, \
> + _width, _upd_ofs, _upd, CLK_SET_RATE_PARENT)
> +
conflicts, these macros are already existed in upstream.
> struct clk *mtk_clk_register_mux(const struct mtk_mux *mux,
> struct regmap *regmap,
> spinlock_t *lock);
> --
> 1.8.1.1.dirty
> _______________________________________________
> Linux-mediatek mailing list
> linux-media...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
