> Hi David > > I did't follow the support for 32768 CPUs in guest without IR support. > > Can you tell me how that is done? Using bits 11-5 of the MSI address bits (the other 7 bits of "Extended Destination ID" that aren't the Remappable Format indicator). And physical addressing mode, which is no loss for external interrupts since they're all unicast dest_Fixed these days anyway. -- dwmw2
- Re: [PATCH v4 06/17] PCI: add SIOV and IMS capability de... Raj, Ashok
- Re: [PATCH v4 06/17] PCI: add SIOV and IMS capabili... Jason Gunthorpe
- RE: [PATCH v4 06/17] PCI: add SIOV and IMS capabili... Tian, Kevin
- Re: [PATCH v4 06/17] PCI: add SIOV and IMS capabili... Raj, Ashok
- Re: [PATCH v4 06/17] PCI: add SIOV and IMS capa... David Woodhouse
- Re: [PATCH v4 06/17] PCI: add SIOV and IMS capabili... Jason Gunthorpe
- Re: [PATCH v4 06/17] PCI: add SIOV and IMS capabili... Christoph Hellwig
- Re: [PATCH v4 06/17] PCI: add SIOV and IMS capa... Raj, Ashok
- Re: [PATCH v4 06/17] PCI: add SIOV and IMS ... Thomas Gleixner
- Re: [PATCH v4 06/17] PCI: add SIOV and ... Raj, Ashok
- Re: [PATCH v4 06/17] PCI: add SIOV... Thomas Gleixner