From: Abel Vesa <[email protected]>
[ Upstream commit b159c63d82ff8ffddc6c6f0eb881b113b36ecad7 ]
According to the latest RM (see Table 5-1. Clock Root Table),
both usdhc root clocks have the parent order as follows:
000 - 25M_REF_CLK
001 - SYSTEM_PLL1_DIV2
010 - SYSTEM_PLL1_CLK
011 - SYSTEM_PLL2_DIV2
100 - SYSTEM_PLL3_CLK
101 - SYSTEM_PLL1_DIV3
110 - AUDIO_PLL2_CLK
111 - SYSTEM_PLL1_DIV8
So the audio_pll2_out and sys3_pll_out have to be swapped.
Fixes: b80522040cd3 ("clk: imx: Add clock driver for i.MX8MQ CCM")
Signed-off-by: Abel Vesa <[email protected]>
Reported-by: Cosmin Stefan Stoica <[email protected]>
Link:
https://lore.kernel.org/r/[email protected]
Reviewed-by: Fabio Estevam <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
Signed-off-by: Sasha Levin <[email protected]>
---
drivers/clk/imx/clk-imx8mq.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
index a64aace213c27..7762c5825e77d 100644
--- a/drivers/clk/imx/clk-imx8mq.c
+++ b/drivers/clk/imx/clk-imx8mq.c
@@ -157,10 +157,10 @@ static const char * const imx8mq_qspi_sels[] =
{"osc_25m", "sys1_pll_400m", "sys
"audio_pll2_out", "sys1_pll_266m",
"sys3_pll_out", "sys1_pll_100m", };
static const char * const imx8mq_usdhc1_sels[] = {"osc_25m", "sys1_pll_400m",
"sys1_pll_800m", "sys2_pll_500m",
- "audio_pll2_out", "sys1_pll_266m",
"sys3_pll_out", "sys1_pll_100m", };
+ "sys3_pll_out", "sys1_pll_266m",
"audio_pll2_out", "sys1_pll_100m", };
static const char * const imx8mq_usdhc2_sels[] = {"osc_25m", "sys1_pll_400m",
"sys1_pll_800m", "sys2_pll_500m",
- "audio_pll2_out", "sys1_pll_266m",
"sys3_pll_out", "sys1_pll_100m", };
+ "sys3_pll_out", "sys1_pll_266m",
"audio_pll2_out", "sys1_pll_100m", };
static const char * const imx8mq_i2c1_sels[] = {"osc_25m", "sys1_pll_160m",
"sys2_pll_50m", "sys3_pll_out", "audio_pll1_out",
"video_pll1_out", "audio_pll2_out",
"sys1_pll_133m", };
--
2.25.1
