On Fri, 25 Sep 2020 15:25:15 +0800 Willy Liu wrote: > There are two chip pins named TXDLY and RXDLY which actually adds the 2ns > delays to TXC and RXC for TXD/RXD latching. These two pins can config via > 4.7k-ohm resistor to 3.3V hw setting, but also config via software setting > (extension page 0xa4 register 0x1c bit13 12 and 11). > > The configuration register definitions from table 13 official PHY datasheet: > PHYAD[2:0] = PHY Address > AN[1:0] = Auto-Negotiation > Mode = Interface Mode Select > RX Delay = RX Delay > TX Delay = TX Delay > SELRGV = RGMII/GMII Selection
Checkpatch says: ERROR: do not set execute permissions for source files #48: FILE: drivers/net/phy/realtek.c ERROR: trailing whitespace #91: FILE: drivers/net/phy/realtek.c:266: +^I * the RX/TX delays otherwise controlled by RXDLY/TXDLY pins. $ total: 2 errors, 0 warnings, 0 checks, 54 lines checked
