On Thu, Sep 03, 2020 at 08:05:03PM +0800, Zhen Lei wrote:
> Add DT bindings for the Hisilicon SD5203 vector interrupt controller.
>
> Signed-off-by: Zhen Lei <thunder.leiz...@huawei.com>
> ---
> .../hisilicon,sd5203-vic.txt | 27 +++++++++++++++++++
Bindings should be in DT schema format now.
> 1 file changed, 27 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/interrupt-controller/hisilicon,sd5203-vic.txt
>
> diff --git
> a/Documentation/devicetree/bindings/interrupt-controller/hisilicon,sd5203-vic.txt
>
> b/Documentation/devicetree/bindings/interrupt-controller/hisilicon,sd5203-vic.txt
> new file mode 100644
> index 000000000000..a08292e868b0
> --- /dev/null
> +++
> b/Documentation/devicetree/bindings/interrupt-controller/hisilicon,sd5203-vic.txt
> @@ -0,0 +1,27 @@
> +Hisilicon SD5203 vector interrupt controller (VIC)
> +
> +Hisilicon SD5203 VIC based on Synopsys DesignWare APB interrupt controller,
> but
> +there's something special:
> +1. The maximum number of irqs supported is 32. The registers ENABLE, MASK and
> + FINALSTATUS are 32 bits.
> +2. There is only one VIC, it's used as primary interrupt controller.
> +
> +Required properties:
> +- compatible: shall be "hisilicon,sd5203-vic"
> +- reg: physical base address of the controller and length of memory mapped
> + region starting with ENABLE_LOW register
> +- interrupt-controller: identifies the node as an interrupt controller
> +- #interrupt-cells: number of cells to encode an interrupt-specifier, shall
> be 1
> +
> +The interrupt sources map to the corresponding bits in the interrupt
> +registers, i.e.
> +- 0 maps to bit 0 of low interrupts,
> +- 1 maps to bit 1 of low interrupts,
> +
> +Example:
> + vic: interrupt-controller@10130000 {
> + compatible = "hisilicon,sd5203-vic";
> + reg = <0x10130000 0x1000>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> --
> 2.26.0.106.g9fadedd
>
>
