On Sun, 2020-08-02 at 07:14 -0700, Doug Smythies wrote:
> On 2020.08.01 16:41 Srinivas Pandruvada wrote:
> > On Tue, 2020-07-28 at 17:13 +0200, Rafael J. Wysocki wrote:
> > > From: Rafael J. Wysocki <rafael.j.wyso...@intel.com>
> > >
> > > Allow intel_pstate to work in the passive mode with HWP enabled
> > > and
> > > make it set the HWP minimum performance limit (HWP floor) to the
> > > P-state value given by the target frequency supplied by the
> > > cpufreq
> > > governor, so as to prevent the HWP algorithm and the CPU
> > > scheduler
> > > from working against each other, at least when the schedutil
> > > governor
> > > is in use, and update the intel_pstate documentation accordingly.
> > >
> > > Among other things, this allows utilization clamps to be taken
> > > into account, at least to a certain extent, when intel_pstate is
> > > in use and makes it more likely that sufficient capacity for
> > > deadline tasks will be provided.
> > >
> > > After this change, the resulting behavior of an HWP system with
> > > intel_pstate in the passive mode should be close to the behavior
> > > of the analogous non-HWP system with intel_pstate in the passive
> > > mode, except that in the frequency range below the base frequency
> > > (ie. the frequency retured by the base_frequency cpufreq
> > > attribute
> > > in sysfs on HWP systems) the HWP algorithm is allowed to go above
> > > the floor P-state set by intel_pstate with or without hardware
> > > coordination of P-states among CPUs in the same package.
> > >
> > Do you mean HWP.req.min will be below base_freq (unless user
> > overrides
> > it)?
>
> No.
Correct. I was just thinking about base_freq relation.
I can set floor above or below base_freq, HWP will reach upto ceiling/
max.
For example:
Floor above base of 0x0d
Busy% Bzy_MHz TSC_MHz M0X774
51.33 3500 1498 0x0000000000000000
99.70 3500 1498 0x00000
0008000270e
2.74 3500 1498 0x000000008000270e
2.92 3500 1498
0x000000008000270e
99.77 3500 1498 0x000000008000270e
99.78 3500
1498 0x000000008000270e
2.98 3500 1498 0x000000008000270e
99.75
3500 1498 0x000000008000270e
3.01 3500 1498 0x00000
0008000270e
Floor Below base of 0x0d
Busy% Bzy_MHz TSC_MHz M0X774
51.33 3500 1498 0x0000000000000000
3.08 3500 1498 0x000000008000270c
99.77 3500 1498 0x000000008000270c
2.87 3500 1498 0x000000008000270c
99.75 3500 1498 0x000000008000270c
2.81 3500 1498 0x000000008000270c
99.76 3500 1498 0x000000008000270c
99.78 3500 1498 0x000000008000270c
2.82 3500 1498 0x000000008000270c
Thanks,
Srinivas
> > With busy workload I see HWP req.min = HWP req.max.
> > The base freq: 1.3GHz (ratio 0x0d), MAX 1C turbo: 3.9GHz (ratio:
> > 0x27)
> > When I monitor MSR 0x774 (HWP_REQ), I see
> > 0x80002727
>
> Yes, that is what I expect to see.
>
> > Normally msr 0x774
> > 0x80002704
>
> That would be "active" mode and the powersave governor, correct?.
> And yes that is what I expect for your processor.
> For mine, load or no load, decoded:
> 0x774: IA32_HWP_REQUEST: CPU 0-5 :
> raw: 80002E08 : 80002E08 : 80002E08 : 80002E08 : 80002E08 :
> 80002E08 :
> min: 8 : 8 : 8 : 8 : 8
> : 8 :
> max: 46 : 46 : 46 : 46 : 46
> : 46 :
> des: 0 : 0 : 0 : 0 : 0
> : 0 :
> epp: 128 : 128 : 128 : 128 : 128
> : 128 :
> act: 0 : 0 : 0 : 0 : 0
> : 0 :
>
> This thread is about passive mode, and myself, I do not expect the
> last byte to be
> 4 (8 for mine) under load.
>
> ... Doug
>
>
