From: Veerabhadrarao Badiganti <vbadi...@codeaurora.org>

On some sc7180 based platforms where external pull is not present on cd-gpio,
this gpio state is getting read as HIGH when sleep config is applied on it.
This is resulting in SDcard rescan after suspend-resume even though SDcard
is not present.

Update cd-gpio sleep config with bais-pull to fix this issue.

Also include xo clock to sdhc clocks list which will be used
in calculating MCLK_FREQ field of DLL_CONFIG2 register.

Signed-off-by: Shaik Sajida Bhanu <sbh...@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/sc7180.dtsi | 12 +++++++-----
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi 
b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index d78a066..8034fcc 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -682,8 +682,9 @@
                        interrupt-names = "hc_irq", "pwr_irq";
 
                        clocks = <&gcc GCC_SDCC1_APPS_CLK>,
-                                       <&gcc GCC_SDCC1_AHB_CLK>;
-                       clock-names = "core", "iface";
+                                       <&gcc GCC_SDCC1_AHB_CLK>,
+                                       <&xo_board>;
+                       clock-names = "core", "iface", "xo";
                        interconnects = <&aggre1_noc MASTER_EMMC &mc_virt 
SLAVE_EBI1>,
                                <&gem_noc MASTER_APPSS_PROC &config_noc 
SLAVE_EMMC_CFG>;
                        interconnect-names = "sdhc-ddr","cpu-sdhc";
@@ -1819,7 +1820,7 @@
 
                                pinconf-sd-cd {
                                        pins = "gpio69";
-                                       bias-disable;
+                                       bias-pull-up;
                                        drive-strength = <2>;
                                };
                        };
@@ -2481,8 +2482,9 @@
                        interrupt-names = "hc_irq", "pwr_irq";
 
                        clocks = <&gcc GCC_SDCC2_APPS_CLK>,
-                                       <&gcc GCC_SDCC2_AHB_CLK>;
-                       clock-names = "core", "iface";
+                                       <&gcc GCC_SDCC2_AHB_CLK>,
+                                       <&xo_board>;
+                       clock-names = "core", "iface", "xo";
 
                        interconnects = <&aggre1_noc MASTER_SDCC_2 &mc_virt 
SLAVE_EBI1>,
                                <&gem_noc MASTER_APPSS_PROC &config_noc 
SLAVE_SDCC_2>;
-- 
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