tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master head: 4ebf8d7649cd86c41c41bf48da4b7761da2d5009 commit: 6e7674c3c6df565ab47d02b4f2e608e3477cdf86 memory: Add DMC driver for Exynos5422 date: 10 months ago config: arm-randconfig-r026-20200717 (attached as .config) compiler: arm-linux-gnueabi-gcc (GCC) 9.3.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross git checkout 6e7674c3c6df565ab47d02b4f2e608e3477cdf86 # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=arm
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <l...@intel.com>
All warnings (new ones prefixed by >>):
drivers/memory/samsung/exynos5422-dmc.c: In function
'exynos5_switch_timing_regs':
>> drivers/memory/samsung/exynos5422-dmc.c:216:6: warning: variable 'ret' set
>> but not used [-Wunused-but-set-variable]
216 | int ret;
| ^~~
drivers/memory/samsung/exynos5422-dmc.c: At top level:
drivers/memory/samsung/exynos5422-dmc.c:736:1: warning: no previous
prototype for 'exynos5_dmc_align_init_freq' [-Wmissing-prototypes]
736 | exynos5_dmc_align_init_freq(struct exynos5_dmc *dmc,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~
vim +/ret +216 drivers/memory/samsung/exynos5422-dmc.c
199
200 /**
201 * exynos5_switch_timing_regs() - Changes bank register set for DRAM
timings
202 * @dmc: device for which the new settings is going to be applied
203 * @set: boolean variable passing set value
204 *
205 * Changes the register set, which holds timing parameters.
206 * There is two register sets: 0 and 1. The register set 0
207 * is used in normal operation when the clock is provided from main PLL.
208 * The bank register set 1 is used when the main PLL frequency is going
to be
209 * changed and the clock is taken from alternative, stable source.
210 * This function switches between these banks according to the
211 * currently used clock source.
212 */
213 static void exynos5_switch_timing_regs(struct exynos5_dmc *dmc, bool
set)
214 {
215 unsigned int reg;
> 216 int ret;
217
218 ret = regmap_read(dmc->clk_regmap, CDREX_LPDDR3PHY_CON3, ®);
219
220 if (set)
221 reg |= EXYNOS5_TIMING_SET_SWI;
222 else
223 reg &= ~EXYNOS5_TIMING_SET_SWI;
224
225 regmap_write(dmc->clk_regmap, CDREX_LPDDR3PHY_CON3, reg);
226 }
227
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0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org
.config.gz
Description: application/gzip
