On Mon, 13 Jul 2020, Xu Yilun wrote: > This patch implements the basic functions of the BMC chip for some Intel > FPGA PCIe Acceleration Cards (PAC). The BMC is implemented using the > intel max10 CPLD. > > This BMC chip is connected to FPGA by a SPI bus. To provide reliable > register access from FPGA, an Avalon Memory-Mapped (Avmm) transaction > protocol over the SPI bus is used between host and slave. > > This driver implements the basic register access with the regmap framework. > The mfd cells array is empty now as a placeholder. > > Signed-off-by: Xu Yilun <yilun...@intel.com> > Signed-off-by: Wu Hao <hao...@intel.com> > Signed-off-by: Matthew Gerlach <matthew.gerl...@linux.intel.com> > Signed-off-by: Russ Weight <russell.h.wei...@intel.com> > Signed-off-by: Tom Rix <t...@redhat.com> > --- > .../ABI/testing/sysfs-driver-intel-m10-bmc | 15 + > drivers/mfd/Kconfig | 13 + > drivers/mfd/Makefile | 3 + > drivers/mfd/intel-m10-bmc-main.c | 176 ++++
> drivers/mfd/intel-spi-avmm.c | 904 > +++++++++++++++++++++ This does not belong in MFD. Please consider moving it to drivers/spi. > drivers/mfd/intel-spi-avmm.h | 35 + > include/linux/mfd/intel-m10-bmc.h | 57 ++ > 7 files changed, 1203 insertions(+) > create mode 100644 Documentation/ABI/testing/sysfs-driver-intel-m10-bmc > create mode 100644 drivers/mfd/intel-m10-bmc-main.c > create mode 100644 drivers/mfd/intel-spi-avmm.c > create mode 100644 drivers/mfd/intel-spi-avmm.h > create mode 100644 include/linux/mfd/intel-m10-bmc.h -- Lee Jones [李琼斯] Senior Technical Lead - Developer Services Linaro.org │ Open source software for Arm SoCs Follow Linaro: Facebook | Twitter | Blog
