[PATCH v4 6/9] mips: bmips: dts: add BCM6362 reset controller support

[Álvaro Fernández Rojas]

BCM6362 SoCs have a reset controller for certain components.

Signed-off-by: Álvaro Fernández Rojas <nolt...@gmail.com>
Acked-by: Florian Fainelli <f.faine...@gmail.com>
---
 v4: no changes.
 v3: add reset controller definitions header file.
 v2: no changes.

 arch/mips/boot/dts/brcm/bcm6362.dtsi      |  6 ++++++
 include/dt-bindings/reset/bcm6362-reset.h | 22 ++++++++++++++++++++++
 2 files changed, 28 insertions(+)
 create mode 100644 include/dt-bindings/reset/bcm6362-reset.h

diff --git a/arch/mips/boot/dts/brcm/bcm6362.dtsi 
b/arch/mips/boot/dts/brcm/bcm6362.dtsi
index 8ae6981735b8..443af6b4c838 100644
--- a/arch/mips/boot/dts/brcm/bcm6362.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm6362.dtsi
@@ -70,6 +70,12 @@ reboot: syscon-reboot@10000008 {
                        mask = <0x1>;
                };
 
+               periph_rst: reset-controller@10000010 {
+                       compatible = "brcm,bcm6345-reset";
+                       reg = <0x10000010 0x4>;
+                       #reset-cells = <1>;
+               };
+
                periph_intc: interrupt-controller@10000020 {
                        compatible = "brcm,bcm6345-l1-intc";
                        reg = <0x10000020 0x10>,
diff --git a/include/dt-bindings/reset/bcm6362-reset.h 
b/include/dt-bindings/reset/bcm6362-reset.h
new file mode 100644
index 000000000000..7ebb0546e0ab
--- /dev/null
+++ b/include/dt-bindings/reset/bcm6362-reset.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __DT_BINDINGS_RESET_BCM6362_H
+#define __DT_BINDINGS_RESET_BCM6362_H
+
+#define BCM6362_RST_SPI                0
+#define BCM6362_RST_IPSEC      1
+#define BCM6362_RST_EPHY       2
+#define BCM6362_RST_SAR                3
+#define BCM6362_RST_ENETSW     4
+#define BCM6362_RST_USBD       5
+#define BCM6362_RST_USBH       6
+#define BCM6362_RST_PCM                7
+#define BCM6362_RST_PCIE_CORE  8
+#define BCM6362_RST_PCIE       9
+#define BCM6362_RST_PCIE_EXT   10
+#define BCM6362_RST_WLAN_SHIM  11
+#define BCM6362_RST_DDR_PHY    12
+#define BCM6362_RST_FAP                13
+#define BCM6362_RST_WLAN_UBUS  14
+
+#endif /* __DT_BINDINGS_RESET_BCM6362_H */
-- 
2.27.0