On Thu, Oct 17, 2019 at 11:08 PM Christoph Hellwig <h...@lst.de> wrote:
>
> When running in M-mode we can't use the SBI to set the timer, and
> don't have access to the time CSR as that usually is emulated by
> M-mode. Instead provide code that directly accesses the MMIO for
> the timer.
>
> Signed-off-by: Christoph Hellwig <h...@lst.de>
> ---
> arch/riscv/include/asm/sbi.h | 3 ++-
> arch/riscv/include/asm/timex.h | 19 +++++++++++++++++--
> drivers/clocksource/timer-riscv.c | 21 +++++++++++++++++----
> 3 files changed, 36 insertions(+), 7 deletions(-)
>
> diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
> index 0cb74eccc73f..a4774bafe033 100644
> --- a/arch/riscv/include/asm/sbi.h
> +++ b/arch/riscv/include/asm/sbi.h
> @@ -95,7 +95,8 @@ static inline void sbi_remote_sfence_vma_asid(const
> unsigned long *hart_mask,
> SBI_CALL_4(SBI_REMOTE_SFENCE_VMA_ASID, hart_mask, start, size, asid);
> }
> #else /* CONFIG_RISCV_SBI */
> -/* stub to for code is only reachable under IS_ENABLED(CONFIG_RISCV_SBI): */
> +/* stubs to for code is only reachable under IS_ENABLED(CONFIG_RISCV_SBI): */
> +void sbi_set_timer(uint64_t stime_value);
> void sbi_remote_fence_i(const unsigned long *hart_mask);
> #endif /* CONFIG_RISCV_SBI */
> #endif /* _ASM_RISCV_SBI_H */
> diff --git a/arch/riscv/include/asm/timex.h b/arch/riscv/include/asm/timex.h
> index c7ef131b9e4c..e17837d61667 100644
> --- a/arch/riscv/include/asm/timex.h
> +++ b/arch/riscv/include/asm/timex.h
> @@ -7,12 +7,25 @@
> #define _ASM_RISCV_TIMEX_H
>
> #include <asm/csr.h>
> +#include <asm/io.h>
>
> typedef unsigned long cycles_t;
>
> +extern u64 __iomem *riscv_time_val;
> +extern u64 __iomem *riscv_time_cmp;
> +
> +#ifdef CONFIG_64BIT
> +#define mmio_get_cycles() readq_relaxed(riscv_time_val)
> +#else
> +#define mmio_get_cycles() readl_relaxed(riscv_time_val)
> +#define mmio_get_cycles_hi() readl_relaxed(((u32 *)riscv_time_val) + 1)
> +#endif
> +
> static inline cycles_t get_cycles(void)
> {
> - return csr_read(CSR_TIME);
> + if (IS_ENABLED(CONFIG_RISCV_SBI))
> + return csr_read(CSR_TIME);
> + return mmio_get_cycles();
> }
> #define get_cycles get_cycles
>
> @@ -24,7 +37,9 @@ static inline u64 get_cycles64(void)
> #else /* CONFIG_64BIT */
> static inline u32 get_cycles_hi(void)
> {
> - return csr_read(CSR_TIMEH);
> + if (IS_ENABLED(CONFIG_RISCV_SBI))
> + return csr_read(CSR_TIMEH);
> + return mmio_get_cycles_hi();
> }
>
> static inline u64 get_cycles64(void)
> diff --git a/drivers/clocksource/timer-riscv.c
> b/drivers/clocksource/timer-riscv.c
> index 5d2fdc3e28a9..2b9fbc4ebe49 100644
> --- a/drivers/clocksource/timer-riscv.c
> +++ b/drivers/clocksource/timer-riscv.c
> @@ -3,9 +3,9 @@
> * Copyright (C) 2012 Regents of the University of California
> * Copyright (C) 2017 SiFive
> *
> - * All RISC-V systems have a timer attached to every hart. These timers can
> be
> - * read from the "time" and "timeh" CSRs, and can use the SBI to setup
> - * events.
> + * All RISC-V systems have a timer attached to every hart. These timers can
> + * either be read from the "time" and "timeh" CSRs, and can use the SBI to
> + * setup events, or directly accessed using MMIO registers.
> */
> #include <linux/clocksource.h>
> #include <linux/clockchips.h>
> @@ -13,14 +13,27 @@
> #include <linux/delay.h>
> #include <linux/irq.h>
> #include <linux/sched_clock.h>
> +#include <linux/io-64-nonatomic-lo-hi.h>
> #include <asm/smp.h>
> #include <asm/sbi.h>
>
> +u64 __iomem *riscv_time_cmp;
> +u64 __iomem *riscv_time_val;
> +
> +static inline void mmio_set_timer(u64 val)
> +{
> + writeq_relaxed(val,
> + riscv_time_cmp + cpuid_to_hartid_map(smp_processor_id()));
> +}
> +
> static int riscv_clock_next_event(unsigned long delta,
> struct clock_event_device *ce)
> {
> csr_set(CSR_XIE, XIE_XTIE);
> - sbi_set_timer(get_cycles64() + delta);
> + if (IS_ENABLED(CONFIG_RISCV_SBI))
> + sbi_set_timer(get_cycles64() + delta);
> + else
> + mmio_set_timer(get_cycles64() + delta);
> return 0;
> }
>
> --
> 2.20.1
>
>
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LGTM.
Reviewed-by: Anup Patel <a...@brainfault.org>
Regards,
Anup
