----- On Sep 6, 2019, at 3:41 AM, Peter Zijlstra pet...@infradead.org wrote:
> On Thu, Sep 05, 2019 at 11:12:59PM -0400, Mathieu Desnoyers wrote:
>> When the prev and next task's mm change, switch_mm() provides the core
>> serializing guarantees before returning to usermode. The only case
>> where an explicit core serialization is needed is when the scheduler
>> keeps the same mm for prev and next.
>>
>> Suggested-by: Oleg Nesterov <o...@redhat.com>
>> Signed-off-by: Mathieu Desnoyers <mathieu.desnoy...@efficios.com>
>> Cc: "Paul E. McKenney" <paul...@linux.ibm.com>
>> Cc: Peter Zijlstra <pet...@infradead.org>
>> Cc: Oleg Nesterov <o...@redhat.com>
>> Cc: "Eric W. Biederman" <ebied...@xmission.com>
>> Cc: Linus Torvalds <torva...@linux-foundation.org>
>> Cc: Russell King - ARM Linux admin <li...@armlinux.org.uk>
>> Cc: Chris Metcalf <cmetc...@ezchip.com>
>> Cc: Christoph Lameter <c...@linux.com>
>> Cc: Kirill Tkhai <tk...@yandex.ru>
>> Cc: Mike Galbraith <efa...@gmx.de>
>> Cc: Thomas Gleixner <t...@linutronix.de>
>> Cc: Ingo Molnar <mi...@kernel.org>
>> ---
>> include/linux/sched/mm.h | 2 ++
>> 1 file changed, 2 insertions(+)
>>
>> diff --git a/include/linux/sched/mm.h b/include/linux/sched/mm.h
>> index 4a7944078cc3..8557ec664213 100644
>> --- a/include/linux/sched/mm.h
>> +++ b/include/linux/sched/mm.h
>> @@ -362,6 +362,8 @@ enum {
>>
>> static inline void membarrier_mm_sync_core_before_usermode(struct mm_struct
>> *mm)
>> {
>> + if (current->mm != mm)
>> + return;
>> if (likely(!(atomic_read(&mm->membarrier_state) &
>> MEMBARRIER_STATE_PRIVATE_EXPEDITED_SYNC_CORE)))
>> return;
>
> So SYNC_CORE is about I$ coherency and funny thing like that. Now it
> seems 'natural' that if we flip the address space, that I$ also gets
> wiped/updated, because the whole text mapping changes.
>
> But did we just assume that, or did we verify the truth of this? (I'm
> just being paranoid here)
We have documented those here:
Documentation/features/sched/membarrier-sync-core/arch-support.txt
For instance, x86:
# * x86
#
# x86-32 uses IRET as return from interrupt, which takes care of the IPI.
# However, it uses both IRET and SYSEXIT to go back to user-space. The IRET
# instruction is core serializing, but not SYSEXIT.
#
# x86-64 uses IRET as return from interrupt, which takes care of the IPI.
# However, it can return to user-space through either SYSRETL (compat code),
# SYSRETQ, or IRET.
#
# Given that neither SYSRET{L,Q}, nor SYSEXIT, are core serializing, we rely
# instead on write_cr3() performed by switch_mm() to provide core serialization
# after changing the current mm, and deal with the special case of kthread ->
# uthread (temporarily keeping current mm into active_mm) by issuing a
# sync_core_before_usermode() in that specific case.
I've also made sure x86 switch_mm_irqs_off() has the following comment,
just in case someone too keen on optimizing away the CR3 write would
forget to look at arch-support.txt:
/*
* The membarrier system call requires a full memory barrier and
* core serialization before returning to user-space, after
* storing to rq->curr. Writing to CR3 provides that full
* memory barrier and core serializing instruction.
*/
In the case of arm/arm64, they have no requirement on switch_mm():
# * arm/arm64
#
# Rely on implicit context synchronization as a result of exception return
# when returning from IPI handler, and when returning to user-space.
Thanks,
Mathieu
--
Mathieu Desnoyers
EfficiOS Inc.
http://www.efficios.com
