Hello, Martin Blumenstingl wrote: > The mainline PCIe PHY driver has it's own devicetree node. Update the > clock alias so the mainline driver finds the clocks. > > The first PCIe PHY is located at 0x1f106800 and exists on VRX200, ARX300 > and GRX390. > The second PCIe PHY is located at 0x1f700400 and exists on ARX300 and > GRX390. > The third PCIe PHY is located at 0x1f106a00 and exists onl on GRX390. > Lantiq's board support package (called "UGW") names these registers > "PDI".
Applied to mips-next. > commit ed90302be64a > https://git.kernel.org/mips/c/ed90302be64a > > Signed-off-by: Martin Blumenstingl <martin.blumensti...@googlemail.com> > Signed-off-by: Paul Burton <paul.bur...@mips.com> Thanks, Paul [ This message was auto-generated; if you believe anything is incorrect then please email paul.bur...@mips.com to report it. ]
