Commit-ID:  773b2f30a3fc026f3ed121a8b945b0ae19b64ec5
Gitweb:     https://git.kernel.org/tip/773b2f30a3fc026f3ed121a8b945b0ae19b64ec5
Author:     Tony W Wang-oc <tonywwang...@zhaoxin.com>
AuthorDate: Tue, 18 Jun 2019 08:37:14 +0000
Committer:  Thomas Gleixner <t...@linutronix.de>
CommitDate: Sat, 22 Jun 2019 11:45:57 +0200

ACPI, x86: Add Zhaoxin processors support for NONSTOP TSC

Zhaoxin CPUs have NONSTOP TSC feature, so enable the ACPI
driver support for it.

Signed-off-by: Tony W Wang-oc <tonywwang...@zhaoxin.com>
Signed-off-by: Thomas Gleixner <t...@linutronix.de>
Cc: "h...@zytor.com" <h...@zytor.com>
Cc: "gre...@linuxfoundation.org" <gre...@linuxfoundation.org>
Cc: "r...@rjwysocki.net" <r...@rjwysocki.net>
Cc: "l...@kernel.org" <l...@kernel.org>
Cc: David Wang <davidw...@zhaoxin.com>
Cc: "Cooper Yan(BJ-RD)" <cooper...@zhaoxin.com>
Cc: "Qiyuan Wang(BJ-RD)" <qiyuanw...@zhaoxin.com>
Cc: "Herry Yang(BJ-RD)" <herryy...@zhaoxin.com>
Link: https://lkml.kernel.org/r/d1cfd937dabc44518d42038b55522...@zhaoxin.com

---
 drivers/acpi/acpi_pad.c       | 1 +
 drivers/acpi/processor_idle.c | 1 +
 2 files changed, 2 insertions(+)

diff --git a/drivers/acpi/acpi_pad.c b/drivers/acpi/acpi_pad.c
index 6b3f1217a237..e7dc0133f817 100644
--- a/drivers/acpi/acpi_pad.c
+++ b/drivers/acpi/acpi_pad.c
@@ -64,6 +64,7 @@ static void power_saving_mwait_init(void)
        case X86_VENDOR_HYGON:
        case X86_VENDOR_AMD:
        case X86_VENDOR_INTEL:
+       case X86_VENDOR_ZHAOXIN:
                /*
                 * AMD Fam10h TSC will tick in all
                 * C/P/S0/S1 states when this bit is set.
diff --git a/drivers/acpi/processor_idle.c b/drivers/acpi/processor_idle.c
index e387a258d649..ed56c6d20b08 100644
--- a/drivers/acpi/processor_idle.c
+++ b/drivers/acpi/processor_idle.c
@@ -196,6 +196,7 @@ static void tsc_check_state(int state)
        case X86_VENDOR_AMD:
        case X86_VENDOR_INTEL:
        case X86_VENDOR_CENTAUR:
+       case X86_VENDOR_ZHAOXIN:
                /*
                 * AMD Fam10h TSC will tick in all
                 * C/P/S0/S1 states when this bit is set.

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