On Thu, Apr 18, 2019 at 10:54:19AM -0400, Waiman Long wrote:
> On 04/18/2019 10:40 AM, Peter Zijlstra wrote:
> > Having more CPUs than that is not impossible these days.
> >
>
> Having more than 32k CPUs contending for the same cacheline will be
> horribly slow.
No question about that.
> >> How about disabling preemption before fetch_all and re-enable
> >> it afterward to address the latter concern?
> > Performance might be an issue, look at what preempt_disable() +
> > preempt_enable() generate for ARM64 for example. That's not particularly
> > pretty.
>
> That is just for the preempt kernel. Right? Thinking about it some more,
> the above scenario is less likely to happen for CONFIG_PREEMPT_VOLUNTARY
> kernel and the preempt_disable cost will be lower.
Depends a bit on what specific CONFIG knobs are used. IIRC something
like NOHZ_FULL will also select PREEMPT_COUNT, it will just not have the
actual preemption calls in.
> A preempt RT kernel is less likely to run on system with many CPUs
> anyway. We could make that a conifg option as well in a follow-on
> patch and let the distributors decide.
RT has a whole different rwsem implementation anyway, so we don't need
to worry about them.
> >> I have no solution for the first case, though.
> > A cmpxchg() loop can fix this, but that again has performance
> > implications like you mentioned a while back.
I thought of a horrible horrible alternative:
union rwsem_count {
struct { /* assuming LP64-LE */
unsigned short other[3];
unsigned short readers;
};
unsigned long value;
};
void down_read(struct rw_semaphore *sem)
{
union rwsem_count c;
unsigned short o;
c.value = atomic_long_read(&sem->count);
c.readers++;
if (!c.readers || (c.value & RWSEM_FLAG_WRITER))
goto slow;
o = xchg(&((union rwsem_count *)sem)->readers, c.readers);
if (o != c.readers-1) {
c.value = atomic_long_fetch_add(&sem->count, o-(c.readers-1));
} else {
c.value = atomic_long_read(&sem->count);
c.readers = o + 1;
}
if (!(c.value & RWSEM_FLAG_WRITER))
return;
slow:
rwsem_down_read_slow(sem, c.value);
}
It is deterministic in that is has at most 2 unconditional atomic ops,
no cmpxchg loop, and a best case of a single op.
