"Suthikulpanit, Suravee" <suravee.suthikulpa...@amd.com> writes:
> Only clear the valid bit when invalidate logical APIC id entry.
> The current logic clear the valid bit, but also set the rest of
> the bits (including reserved bits) to 1.
>
> Fixes: 98d90582be2e ('svm: Fix AVIC DFR and LDR handling')
> Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpa...@amd.com>
> ---
> arch/x86/kvm/svm.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
> index 7a4ce1a22ca0..f4fb766e474c 100644
> --- a/arch/x86/kvm/svm.c
> +++ b/arch/x86/kvm/svm.c
> @@ -4640,7 +4640,7 @@ static void avic_invalidate_logical_id_entry(struct
> kvm_vcpu *vcpu)
> u32 *entry = avic_get_logical_id_entry(vcpu, svm->ldr_reg, flat);
>
> if (entry)
> - WRITE_ONCE(*entry, (u32) ~AVIC_LOGICAL_ID_ENTRY_VALID_MASK);
> + WRITE_ONCE(*entry, (u32)(*entry &
> ~AVIC_LOGICAL_ID_ENTRY_VALID_MASK));
I'm not sure how important this is, but this change creates a tiny time
window between reading from *entry and writing there. Should we use
atomic bitops instead?
> }
>
> static int avic_handle_ldr_update(struct kvm_vcpu *vcpu)
--
Vitaly
