> > This patch adds DMA support for Tegra I2C.
> >
> > Tegra I2C TX and RX FIFO depth is 8 words. PIO mode is used for
> > transfer size of the max FIFO depth and DMA mode is used for transfer
> > size higher than max FIFO depth to save CPU overhead.
> >
> > PIO mode needs full intervention of CPU to fill or empty FIFO's and
> > also need to service multiple data requests interrupt for the same
> > transaction. This adds delay between data bytes of the same transfer
> > when CPU is fully loaded and some slave devices has internal timeout
> > for no bus activity and stops transaction to avoid bus hang. DMA mode
> > is helpful in such cases.
> >
> > DMA mode is also helpful for Large transfers during downloading or
> > uploading FW over I2C to some external devices.
> >
> > Signed-off-by: Sowjanya Komatineni <skomatin...@nvidia.com>
> > ---
>
>
> > +static int tegra_i2c_init_dma(struct tegra_i2c_dev *i2c_dev) {
> > + struct dma_chan *dma_chan;
> > + u32 *dma_buf;
> > + dma_addr_t dma_phys;
> > + int err = 0;
> > +
> > + if (!IS_ENABLED(CONFIG_TEGRA20_APB_DMA))
> > + return -ENODEV;
>
> Another detail is that we need to keep older kernels working on T186+ after
> its device-tree will get the "dmas" property, device-tree changes shall be
> backwards-compatible with older kernels. Hence we need to check that platform
> actually wants the APB DMA driver, otherwise T186+ will be failing with
> -EPROBE_DEFER.
Yes, that will be a separate patch later for adding DMA support for Tegra186
and later chips once we check on GPCDMA upstream
