On January 10, 2019 5:34:21 PM PST, Sean Christopherson <sean.j.christopher...@intel.com> wrote: >On Thu, Jan 10, 2019 at 04:59:55PM -0800, h...@zytor.com wrote: >> On January 10, 2019 9:42:57 AM PST, Sean Christopherson ><sean.j.christopher...@intel.com> wrote: >> >On Thu, Jan 10, 2019 at 12:32:43PM -0500, Steven Rostedt wrote: >> >> On Thu, 10 Jan 2019 11:20:04 -0600 >> >> Josh Poimboeuf <jpoim...@redhat.com> wrote: >> >> >> >> >> >> > > While I can't find a reason for hypervisors to emulate this >> >instruction, >> >> > > smarter people might find ways to turn it into a security >> >exploit. >> >> > >> >> > Interesting point... but I wonder if it's a realistic concern. >> >BTW, >> >> > text_poke_bp() also relies on undocumented behavior. >> >> >> >> But we did get an official OK from Intel that it will work. Took a >> >bit >> >> of arm twisting to get them to do so, but they did. And it really >is >> >> pretty robust. >> > >> >Did we (they?) list any caveats for this behavior? E.g. I'm fairly >> >certain atomicity guarantees go out the window if WC memtype is >used. >> >> If you run code from non-WB memory, all bets are off and you better >> not be doing cross-modifying code. > >I wasn't thinking of running code from non-WB, but rather running code >in WB while doing a CMC write via WC.
Same thing. Don't do that. -- Sent from my Android device with K-9 Mail. Please excuse my brevity.
