On Thu, Jan 10, 2019 at 08:48:31PM +0000, Nadav Amit wrote: > > On Jan 10, 2019, at 12:32 PM, Josh Poimboeuf <jpoim...@redhat.com> wrote: > > > > On Thu, Jan 10, 2019 at 07:45:26PM +0000, Nadav Amit wrote: > >>>> I’m not GCC expert either and writing this code was not making me full of > >>>> joy, etc.. I’ll be happy that my code would be reviewed, but it does > >>>> work. I > >>>> don’t think an early pass is needed, as long as hardware registers were > >>>> not > >>>> allocated. > >>>> > >>>>> Would it work with more than 5 arguments, where args get passed on the > >>>>> stack? > >>>> > >>>> It does. > >>>> > >>>>> At the very least, it would (at least partially) defeat the point of the > >>>>> callee-saved paravirt ops. > >>>> > >>>> Actually, I think you can even deal with callee-saved functions and > >>>> remove > >>>> all the (terrible) macros. You would need to tell the extension not to > >>>> clobber the registers through a new attribute. > >>> > >>> Ok, it does sound interesting then. I assume you'll be sharing the > >>> code? > >> > >> Of course. If this what is going to convince, I’ll make a small version for > >> PV callee-saved first. > > > > It wasn't *only* the PV callee-saved part which interested me, so if you > > already have something which implements the other parts, I'd still like > > to see it. > > Did you have a look at > https://lore.kernel.org/lkml/20181231072112.21051-4-na...@vmware.com/ ? > > See the changes to x86_call_markup_plugin.c . > > The missing part (that I just finished but need to cleanup) is attributes > that allow you to provide key and dynamically enable the patching.
Aha, so it's the basically the same plugin you had for optpolines. I missed that. I'll need to stare at the code for a little bit. > >>>>> What if we just used a plugin in a simpler fashion -- to do call site > >>>>> alignment, if necessary, to ensure the instruction doesn't cross > >>>>> cacheline boundaries. This could be done in a later pass, with no side > >>>>> effects other than code layout. And it would allow us to avoid > >>>>> breakpoints altogether -- again, assuming somebody can verify that > >>>>> intra-cacheline call destination writes are atomic with respect to > >>>>> instruction decoder reads. > >>>> > >>>> The plugin should not be able to do so. Layout of the bytecode is done by > >>>> the assembler, so I don’t think a plugin would help you with this one. > >>> > >>> Actually I think we could use .bundle_align_mode for this purpose: > >>> > >>> https://na01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fsourceware.org%2Fbinutils%2Fdocs-2.31%2Fas%2FBundle-directives.html&data=02%7C01%7Cnamit%40vmware.com%7Cbc4dcc541474462da00b08d6773ab61f%7Cb39138ca3cee4b4aa4d6cd83d9dd62f0%7C0%7C0%7C636827491388051263&sdata=HZNPN4UygwQCqsX8dOajaNeDZyy1O0O4cYeSwu%2BIdO0%3D&reserved=0 > >> > >> Hm… I don’t understand what you have in mind (i.e., when would this > >> assembly directives would be emitted). > > > > For example, it could replace > > > > callq ____static_call_tramp_my_key > > > > with > > > > .bundle_align_mode 6 > > callq ____static_call_tramp_my_key > > .bundle_align_mode 0 > > > > which ensures the instruction is within a cache line, aligning it with > > NOPs if necessary. That would allow my current implementation to > > upgrade out-of-line calls to inline calls 100% of the time, instead of > > 95% of the time. > > Heh. I almost wrote based no the feature description that this will add > unnecessary padding no matter what, but actually (experimentally) it works > well… Yeah, based on the poorly worded docs, I made the same assumption, until I tried it. -- Josh
