Hi Lorenzo, -----Original Message----- From: Lorenzo Pieralisi <lorenzo.pieral...@arm.com> Sent: 2018年11月30日 18:55 To: Xiaowei Bao <xiaowei....@nxp.com> Cc: bhelg...@google.com; robh...@kernel.org; mark.rutl...@arm.com; shawn...@kernel.org; Leo Li <leoyang...@nxp.com>; kis...@ti.com; a...@arndb.de; gre...@linuxfoundation.org; M.h. Lian <minghuan.l...@nxp.com>; Mingkai Hu <mingkai...@nxp.com>; Roy Zang <roy.z...@nxp.com>; kstew...@linuxfoundation.org; cyrille.pitc...@free-electrons.com; pombreda...@nexb.com; shawn....@rock-chips.com; niklas.cas...@axis.com; linux-...@vger.kernel.org; devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org; linuxppc-...@lists.ozlabs.org Subject: Re: [PATCHv2 3/6] PCI: layerscape: Add the EP mode support
On Mon, Nov 05, 2018 at 04:46:50PM +0800, Xiaowei Bao wrote: > Add the EP mode support. > > Signed-off-by: Xiaowei Bao <xiaowei....@nxp.com> > --- > v2: > - Add the SoC specific compatibles. > > .../devicetree/bindings/pci/layerscape-pci.txt | 3 +++ > 1 files changed, 3 insertions(+), 0 deletions(-) Wrong commit $SUBJECT, this is not PCI code, it is a DT binding update, I will have a look at the rest of the series to see if I can update this patch or you will do it with the next respin. Lorenzo [Xiaowei Bao] HI Lorenzo, thanks a lot, I will send V3 patch to modify the commits. > diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt > b/Documentation/devicetree/bindings/pci/layerscape-pci.txt > index 66df1e8..9c090c7 100644 > --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt > +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt > @@ -13,12 +13,15 @@ information. > > Required properties: > - compatible: should contain the platform identifier such as: > + RC mode: > "fsl,ls1021a-pcie", "snps,dw-pcie" > "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", "snps,dw-pcie" > "fsl,ls2088a-pcie" > "fsl,ls1088a-pcie" > "fsl,ls1046a-pcie" > "fsl,ls1012a-pcie" > + EP mode: > + "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep" > - reg: base addresses and lengths of the PCIe controller register blocks. > - interrupts: A list of interrupt outputs of the controller. Must contain an > entry for each entry in the interrupt-names property. > -- > 1.7.1 >
