On Mon, Sep 10, 2018 at 7:19 PM, Christoph Hellwig <h...@infradead.org> wrote: > On Mon, Sep 10, 2018 at 03:45:42PM +0200, Thomas Gleixner wrote: >> > He has an irqchip that is called from the RISC-V exception handler >> > when the interrupt flag is set in scause and then dispatches to one >> > of: IPI, timer, actual irqchip. >> >> So the per cpu timer is the only per cpu interrupt and that thing is used >> unconditionally, right? > > Yes. external is chained and IPI is still handled explicitly.
On riscv64, there are 64 local interrupts (i.e. per-CPU interrupts). Three of these local interrupts have clearly defined use: 1. Software interrupt (inter-processor interrupt) 2. External interrupt (interrupt from PLIC) 3. Timer interrupt (interrupt from per-CPU timer) Other local interrupts are available for future use. Taking inspiration from ARM world, I had give quite a few examples how these RISC-V local interrupts can be used for other purposes: 1. per-CPU interrupt for per-HART performance monitoring unit 2. interrupt controller virtualizaton extension can use per-CPU interrupts for managing resources (just like ARM GICv2/v3 virt extensions) 3. bus errors can be reported as per-CPU interrupts Considering above, it is better to have a distinct irqchip and irq_domain for all local interrupts (just like this patch). Regards, Anup
