On Mon, Sep 10, 2018 at 03:37:31PM +0200, Thomas Gleixner wrote: > > > Just a few weeks ago you said the contrary: > > > > > > http://lists.infradead.org/pipermail/linux-riscv/2018-August/000943.html > > > > Sigh. Yes. Now that you remind me. > > Just for clarification. I had the impression that Anup was trying to wire > up more than just the timer interrupt, but that doesn't seem to be the > case.
He has an irqchip that is called from the RISC-V exception handler when the interrupt flag is set in scause and then dispatches to one of: IPI, timer, actual irqchip.
