On Sun, Dec 10, 2000 at 01:35:26AM -0500, Victor J. Orlikowski wrote:
> Steven,
>
> One question:
> Do you have MTRR enabled?
> If so, a temporary workaround is to re-compile the kernel with
> it disabled.
To confirm, yes, I do have MTRR's enabled. I'll see if that fixes it...
it hasn't happened in the past (checks uptime) 1 day and 9 hours, so
Out of curiosity, has someone found a reliable way of reproducing this?
> This is getting to be something of an epidemic.
> As I said, AMD's docs state that the write-combining was
> altered in the model and stepping stated. However, I would not
> consider myself *nearly* experienced enough in x86 assembler to start
> playing around with trying to work up a patch.
>
--
-Steven
"Voters decide nothing. Vote counters decide everything."
-Joseph Stalin
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