Steven,
One question:
Do you have MTRR enabled?
If so, a temporary workaround is to re-compile the kernel with
it disabled.
This is getting to be something of an epidemic.
As I said, AMD's docs state that the write-combining was
altered in the model and stepping stated. However, I would not
consider myself *nearly* experienced enough in x86 assembler to start
playing around with trying to work up a patch.
Victor
--
Victor J. Orlikowski
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