A clock gate does not resample the clock signal, it give the same
signal as the parent if enabled, so it can use the duty cycle
passthrough operations
Signed-off-by: Jerome Brunet <jbru...@baylibre.com>
---
drivers/clk/clk-gate.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
index dd82485e09a1..eb6dcebfcd5c 100644
--- a/drivers/clk/clk-gate.c
+++ b/drivers/clk/clk-gate.c
@@ -107,6 +107,8 @@ const struct clk_ops clk_gate_ops = {
.enable = clk_gate_enable,
.disable = clk_gate_disable,
.is_enabled = clk_gate_is_enabled,
+ .set_duty_cycle = __clk_set_duty_cycle_passthrough,
+ .get_duty_cycle = __clk_get_duty_cycle_passthrough,
};
EXPORT_SYMBOL_GPL(clk_gate_ops);
--
2.14.3
