On Fri, Mar 16, 2018 at 3:02 PM, Icenowy Zheng <icen...@aosc.io> wrote:
> The Allwinner H6 SoC have its pin controllers with the first IRQ-capable > GPIO bank at IRQ bank 1 and the second bank at IRQ bank 5. Some > refactors in the sunxi pinctrl framework are needed. > > This commit introduces a IRQ bank conversion function, which replaces > the "(bank_base + bank)" code in IRQ register access. > > Signed-off-by: Icenowy Zheng <icen...@aosc.io> > --- > Extracted in v4. Patch applied with Maxime's ACK. Yours, Linus Walleij
