On Fri, Mar 16, 2018 at 10:02:08PM +0800, Icenowy Zheng wrote: > The Allwinner H6 SoC have its pin controllers with the first IRQ-capable > GPIO bank at IRQ bank 1 and the second bank at IRQ bank 5. Some > refactors in the sunxi pinctrl framework are needed. > > This commit introduces a IRQ bank conversion function, which replaces > the "(bank_base + bank)" code in IRQ register access. > > Signed-off-by: Icenowy Zheng <icen...@aosc.io>
Acked-by: Maxime Ripard <maxime.rip...@bootlin.com> Thanks! Maxime -- Maxime Ripard, Bootlin (formerly Free Electrons) Embedded Linux and Kernel engineering https://bootlin.com
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