On Wed, Jan 24, 2018 at 01:50:52PM +0100, Thomas Gleixner wrote:
> On Tue, 23 Jan 2018, Lyude Paul wrote:
>
> > Hi! Sorry to be the bearer of bad news, but this patch actually seems to
> > break
> > suspending and resuming with nouveau on my machine:
>
> > [ 31.003578] WARNING: CPU: 0 PID: 11523 at kernel/smp.c:291
> > smp_call_function_single+0xdc/0xe0
>
> This warning has absolutely no relationship to that patch.
>
> > [ 31.003592] RIP: 0010:smp_call_function_single+0xdc/0xe0
> > [ 31.003603] ? rdmsr_safe_on_cpu+0x4b/0x70
> > [ 31.003604] rdmsr_safe_on_cpu+0x4b/0x70
> > [ 31.003606] get_block_address.isra.0+0x6e/0xe0
> > [ 31.003607] mce_amd_feature_init+0x63/0x2c0
> > [ 31.003609] mce_syscore_resume+0x1e/0x30
> > [ 31.003611] syscore_resume+0x4b/0x170
> > [ 31.003613] suspend_devices_and_enter+0x608/0x7e0
> > [ 31.003614] pm_suspend+0x315/0x380
> > [ 31.003615] state_store+0x7d/0xe0
> > [ 31.003618] kernfs_fop_write+0xfa/0x180
> > [ 31.003620] __vfs_write+0x23/0x130
> > [ 31.003623] ? SYSC_newfstat+0x29/0x40
> > [ 31.003625] ? _cond_resched+0x15/0x40
> > [ 31.003626] vfs_write+0xad/0x1a0
> > [ 31.003627] SyS_write+0x42/0x90
> > [ 31.003629] entry_SYSCALL_64_fastpath+0x24/0x87
>
> Borislav?
Yeah
cfee4f6f0b20 ("x86/mce/AMD: Read MSRs on the CPU allocating the threshold
blocks")
Yazen CCed.
Non-core banks are accessible only on the node-base CPU or something
like that. But we can't send IPIs with IRQs off, thus the warning.
Yazen, I'm thinking this whole get_block_address() dancing can be
simplified by creating a data structure containing *all* MCi_MISC*
addresses once during boot and then using it instead of reading it from
the MSRs each time.
Also - and I'm wishfully thinking simple here - that structure could
be global as I'd venture a guess that all MISC addresses are the same
system-wide and not node-specific.
But I might be missing something here.
Hmmm.
--
Regards/Gruss,
Boris.
Good mailing practices for 400: avoid top-posting and trim the reply.
