* Kirill A. Shutemov <kirill.shute...@linux.intel.com> wrote:
> This patch prepare decompression code to boot-time switching between 4-
> and 5-level paging.
>
> Signed-off-by: Kirill A. Shutemov <kirill.shute...@linux.intel.com>
> ---
> arch/x86/boot/compressed/head_64.S | 24 ++++++++++++++++++++++++
> 1 file changed, 24 insertions(+)
>
> diff --git a/arch/x86/boot/compressed/head_64.S
> b/arch/x86/boot/compressed/head_64.S
> index b4a5d284391c..09c85e8558eb 100644
> --- a/arch/x86/boot/compressed/head_64.S
> +++ b/arch/x86/boot/compressed/head_64.S
> @@ -288,6 +288,28 @@ ENTRY(startup_64)
> leaq boot_stack_end(%rbx), %rsp
>
> #ifdef CONFIG_X86_5LEVEL
> + /* Preserve rbx across cpuid */
> + movq %rbx, %r8
> +
> + /* Check if leaf 7 is supported */
> + xorl %eax, %eax
> + cpuid
> + cmpl $7, %eax
> + jb lvl5
> +
> + /*
> + * Check if la57 is supported.
> + * The feature is enumerated with CPUID.(EAX=07H, ECX=0):ECX[bit 16]
> + */
> + movl $7, %eax
> + xorl %ecx, %ecx
> + cpuid
> + andl $(1 << 16), %ecx
> + jz lvl5
> +
> + /* Restore rbx */
In (new) x86 asm code we refer to registers in capital letters.
Also, CPUID should be capitalized consistently as well.
Also, LA57 should be capitalized as well.
> + movq %r8, %rbx
> +
> /* Check if 5-level paging has already enabled */
> movq %cr4, %rax
BTW., please also fix the typo in this comment while at it.
Thanks,
Ingo
