On Sun, Aug 27, 2017 at 02:29:26PM +0300, Cyrill Gorcunov wrote: > On Mon, Aug 21, 2017 at 06:29:03PM +0300, Kirill A. Shutemov wrote: > > This patch prepare decompression code to boot-time switching between 4- > > and 5-level paging. > > > > Signed-off-by: Kirill A. Shutemov <[email protected]> > > --- > > arch/x86/boot/compressed/head_64.S | 24 ++++++++++++++++++++++++ > > 1 file changed, 24 insertions(+) > > > > diff --git a/arch/x86/boot/compressed/head_64.S > > b/arch/x86/boot/compressed/head_64.S > > index fbf4c32d0b62..2e362aea3319 100644 > > --- a/arch/x86/boot/compressed/head_64.S > > +++ b/arch/x86/boot/compressed/head_64.S > > @@ -347,6 +347,28 @@ preferred_addr: > > leaq boot_stack_end(%rbx), %rsp > > > > #ifdef CONFIG_X86_5LEVEL > > + /* Preserve rbx across cpuid */ > > + movq %rbx, %r8 > > + > > + /* Check if leaf 7 is supported */ > > + movl $0, %eax > > Use xor instead, it should be shorter > > > + cpuid > > + cmpl $7, %eax > > + jb lvl5 > > + > > + /* > > + * Check if la57 is supported. > > + * The feature is enumerated with CPUID.(EAX=07H, ECX=0):ECX[bit 16] > > + */ > > + movl $7, %eax > > + movl $0, %ecx > > same
Thanks. I'll update it for the next re-spin. -- Kirill A. Shutemov
