Am Mittwoch, 23. August 2017, 16:00:07 CEST schrieb David Wu: > The pins from GPIO1A0 to GPIO1B1 are special, need to recalculate > iomux. And the register offset is larger than the u8 range, so changed > to u32. > > Signed-off-by: David Wu <david...@rock-chips.com>
While I'm still struggling trying to understand why some chip-designer would move these iomux settings into the general SOC_CON registers, this matches the documentation for the rv1108, so Reviewed-by: Heiko Stuebner <he...@sntech.de> Heiko
