Read back the register after setting or clearing a reset bit to make sure that the changes are applied to the reset controller hardware. Theoretically, this avoids the write to stay stuck in a store buffer during the delay of an assert-delay-deassert sequence, and makes sure that the reset really is asserted for the specified duration.
Signed-off-by: Philipp Zabel <p.za...@pengutronix.de> --- drivers/reset/reset-simple.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/reset/reset-simple.c b/drivers/reset/reset-simple.c index 13e7d5559acc9..d98a7e7d802d1 100644 --- a/drivers/reset/reset-simple.c +++ b/drivers/reset/reset-simple.c @@ -39,17 +39,20 @@ static int reset_simple_set(struct reset_controller_dev *rcdev, int reg_width = sizeof(u32); int bank = id / (reg_width * BITS_PER_BYTE); int offset = id % (reg_width * BITS_PER_BYTE); + void __iomem *addr = data->membase + (bank * reg_width); unsigned long flags; u32 reg; spin_lock_irqsave(&data->lock, flags); - reg = readl(data->membase + (bank * reg_width)); + reg = readl(addr); if (assert ^ data->active_low) reg |= BIT(offset); else reg &= ~BIT(offset); - writel(reg, data->membase + (bank * reg_width)); + writel(reg, addr); + /* Read back to make sure the write doesn't linger in a store buffer */ + readl(addr); spin_unlock_irqrestore(&data->lock, flags); -- 2.11.0