On Thu, Jun 15, 2017 at 1:02 PM, Andi Kleen <a...@linux.intel.com> wrote: > On Thu, Jun 15, 2017 at 12:35:39PM -0700, Stephane Eranian wrote: >> On Thu, Jun 15, 2017 at 10:23 AM, Andi Kleen <a...@linux.intel.com> wrote: >> > On Thu, Jun 15, 2017 at 09:44:07AM -0700, Stephane Eranian wrote: >> >> On Thu, Jun 15, 2017 at 8:10 AM, Andi Kleen <a...@linux.intel.com> wrote: >> >> > On Thu, Jun 15, 2017 at 06:56:24AM -0700, Stephane Eranian wrote: >> >> >> This patchs adds a new sample record type called >> >> >> PERF_SAMPLE_SKID_IP. The goal is to record >> >> >> the unmodified interrupted instruction pointer (IP) as seen by >> >> >> the kernel and reflected in the machine state. >> >> > >> >> > Patches look reasonable for me. >> >> > >> >> > If you only cared about branches it would be more natural to model >> >> > it like a 1 entry LBR. That would make a lot more tooling work >> >> > automatically. >> >> > >> >> You'd still have to modify tooling to present correct column headers. >> > >> > Why? It's from/to? >> > >> Ah, yes you are right, but it is not clear to me how you would specify >> this cleanly with the interface. >> Especially in the case where this could be used for non-branch instructions. > > Generally the skid ip is only interesting for instructions that have some > kind of > control flow change, or an exception/interrupt. > True, right now I found use for the control flow changes, but any PEBS enabled event + precise=2 could potentially be useful. > So if it's interesting the headers would be correct. > > Actually it's even correct for non control flow change, because the IP > moves from "FROM" to "TO" ... > Sure. But I am not too fond of tying this to a branch abstraction. You'd have to express this with the perf_events interface.To trigger LBR-style hardware, you'd have to define a new PERF_SAMPLE_BRANCH_SKID_IP of some sort and then you tie this to a branch kind of sampling feature:
$ perf record -j skid_ip -e BR_INST_RETIRED.CONDITIONAL:pp Is what I think you are thinking about.
