On 31/05/2017 19:33, Sudeep Holla wrote: > > > On 31/05/17 17:40, Daniel Lezcano wrote: > >> Hi Sudeep, Lorenzo, >> >> I have been thinking and looking at the domain-idle-state and I don't >> see an obvious connection between what is describing the power domain, >> the cpu idle driver and what we are trying to achieve. >> > > I am not sure what you mean by *connection* above. > > 1. With old flat list of idle states, we should get the cpumask sharing > the idle states from the phandle or something similar. > 2. With new domain-idle-state and hierarchical DT binding, you just need > to infer that from the hierarchy. > >> I would like to suggest something much more simple, register a cpuidle >> driver per cpu, so every cpu can have its own idle definitions, that >> should work for dynamiQ, smp and hmp. The impact on the driver will be >> minimal. >> > > Sounds simple, but not sure if it's scalable on platforms with > relatively large number of CPUs like 48 or 96(e.g. Cavium Thunder
I'm pretty sure it scales, we had the idle states per cpuidle devices and nobody was complaining. But I agree it could be optimized. -- <http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook | <http://twitter.com/#!/linaroorg> Twitter | <http://www.linaro.org/linaro-blog/> Blog
