Michael Ellerman <[EMAIL PROTECTED]> writes: > It's an arch detail whether MSI irqs need to be masked using the PCI > MSI registers.
Agreed. It isn't an arch detail that they need to be unmasked in the pci configuration space. I assume this patch is motivated just to make arch support easier and not for RTAS compatibility reason. > This changes behaviour in that previously we unconditionally masked > all MSIs, eventhough we only ever enable one, whereas now we only > mask the irqs we're using. > > To be super paranoid I have the archs mask the irq before they write > the msi message, just in case the device doesn't respect the MSI enable > bit or MSI is already enabled or something else crazy. > > For MSI-X this might mean we mask the already masked MSI-X on the device, > but that should be harmless. I don't think this patch really makes sense. I think we should mask all possible vectors for msi and msi-x initially in the generic code and then unmask them. If we were trying to support Dave Miller's example of hypervisors that don't let us touch the msi registers I think there would be a point. As it is I think this just makes the code more brittle. Eric - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
