On Mon, Mar 20, 2017 at 12:19 AM, Icenowy Zheng <icen...@aosc.xyz> wrote: > Allwinner H3/V3s/A64 SoCs have a special USB PHY0 that can route to two > controllers: one is MUSB and the other is a EHCI/OHCI pair. > > When it's routed to EHCI/OHCI pair, it will needs a "pmu0" regs to > tweak, like other EHCI/OHCI pairs in Allwinner SoCs. > > Add this to the binding of USB PHYs on Allwinner H3/V3s/A64. > > Signed-off-by: Icenowy Zheng <icen...@aosc.xyz>
Acked-by: Chen-Yu Tsai <w...@csie.org> Please keep acks and review tags from others if you haven't changed the patch.
