On 02/08, Chris Packham wrote:
> The initial implementation in commit e120c17a70e5 ("clk: mvebu: support
> for 98DX3236 SoC") hardcoded a fixed value for the main PLL frequency.
> Port code from the Marvell supplied Linux kernel to support different
> PLL frequencies and provide clock gating support.
>
> Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz>
> ---
Applied to clk-next
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