On Wed, Dec 07, 2016 at 03:04:31PM -0500, Christopher Covington wrote: > From: Shanker Donthineni <shank...@codeaurora.org> > > During a TLB invalidate sequence targeting the inner shareable > domain, Falkor may prematurely complete the DSB before all loads > and stores using the old translation are observed; instruction > fetches are not subject to the conditions of this erratum. > > Signed-off-by: Shanker Donthineni <shank...@codeaurora.org> > Signed-off-by: Christopher Covington <c...@codeaurora.org> > --- > arch/arm64/Kconfig | 10 +++++++++ > arch/arm64/include/asm/cpucaps.h | 3 ++- > arch/arm64/include/asm/tlbflush.h | 43 > +++++++++++++++++++++++++++++++++++++++ > arch/arm64/kernel/cpu_errata.c | 7 +++++++ > arch/arm64/kvm/hyp/tlb.c | 39 ++++++++++++++++++++++++++++++----- > 5 files changed, 96 insertions(+), 6 deletions(-)
Please update Documentation/arm64/silicon-errata.txt respectively. [...] > #include <linux/sched.h> > #include <asm/cputype.h> > +#include <asm/alternative.h> Nit: please keep includes (alphabetically) ordered (at least below the linux/ or asm/ level). [...] > + asm volatile(ALTERNATIVE( > + "nop \n" > + "nop \n", > + "tlbi vmalle1is \n" > + "dsb ish \n", As a general note, perhaps we want a C compatible NOP_ALTERNATIVE() so that the nop case can be implicitly generated for sequences like this. Thanks, Mark.
