From: Stephane Eranian <eran...@google.com>
The offset of the counters for UPI and M2M boxes on Skylake server is
non-standard (8 bytes apart).
This patch introduces a custom flag UNCORE_BOX_FLAG_CTL_OFFS8 to
specially handle it.
Signed-off-by: Stephane Eranian <eran...@google.com>
Signed-off-by: Kan Liang <kan.li...@intel.com>
---
arch/x86/events/intel/uncore.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/x86/events/intel/uncore.h b/arch/x86/events/intel/uncore.h
index 78b9c23..a43175f 100644
--- a/arch/x86/events/intel/uncore.h
+++ b/arch/x86/events/intel/uncore.h
@@ -120,6 +120,7 @@ struct intel_uncore_box {
};
#define UNCORE_BOX_FLAG_INITIATED 0
+#define UNCORE_BOX_FLAG_CTL_OFFS8 1 /* event config registers are 8-byte
apart */
struct uncore_event_desc {
struct kobj_attribute attr;
@@ -172,6 +173,9 @@ static inline unsigned uncore_pci_fixed_ctr(struct
intel_uncore_box *box)
static inline
unsigned uncore_pci_event_ctl(struct intel_uncore_box *box, int idx)
{
+ if (test_bit(UNCORE_BOX_FLAG_CTL_OFFS8, &box->flags))
+ return idx * 8 + box->pmu->type->event_ctl;
+
return idx * 4 + box->pmu->type->event_ctl;
}
--
2.5.5
