Am Dienstag, 2. August 2016, 15:19:58 schrieb Xing Zheng: > Dues to incorrect diagram, we need to fix incorrect bits for > (c/g)pll_aclk_emmc_src: > cpll_aclk_emmc_src --> G6[13] > gpll_aclk_emmc_src --> G6[12] > > Signed-off-by: Xing Zheng <zhengx...@rock-chips.com> > Reviewed-by: Shawn Lin <shawn....@rock-chips.com>
applied to my clk-fixes branch for 4.8 Thanks Heiko
