On 08/08/2016 08:32 PM, Borislav Petkov wrote: > On Mon, Aug 08, 2016 at 03:39:44PM +0000, york sun wrote: >> RFXE is cleared by default. So for most SoCs, this is not even a concern >> at all. But for e500v1, when RIO or PCI are used, this bit is set >> specifically to catch an error by machine check (see commit 4e0e3435). >> This is not the uncorrectable error from DDR. We will be better off to >> let this error happen. > > So I'm reading this: "With this bit set, EDAC driver can't get the > interrupt in case of uncorrectable error. So this bit is cleared in > favor of EDAC." > > AFAIU, it means, RFXE bit remains clear so EDAC will get the interrupt > for the uncorrectable error (UE). So on those !e500v1 systems, EDAC be > handling those UEs. > > Am I close? > > If so, can EDAC handle the UE? >
Yes, for most SoCs RFXE remains cleared. Uncorrectable errors are handled by EDAC. York
